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Scientists smash record in stacking semiconductor transistors for large-area electronics

The six stacks of semiconductors for hybrid complementary metal-oxide semiconductor (CMOS) microchips advances miniaturization and topples the previous record of two stack

2025-10-17
(Press-News.org) King Abdullah University of Science and Technology (KAUST; Saudi Arabia) researchers have set a record in microchip design, achieving the first six-stack hybrid CMOS (complementary metal-oxide semiconductor) for large-area electronics. With no other reported hybrid CMOS exceeding two stacks, the feat marks a new benchmark in integration density and efficiency, opening possibilities in electronic miniaturization and performance. 

Among microchip technologies, CMOS microchips are found in nearly all electronics, from phones and televisions to satellites and medical devices. Compared with conventional silicon chips, hybrid CMOS microchips hold greater promise for large-area electronics. Electronic miniaturization is crucial for flexible electronics, smart health, and the Internet of Things, but current design approaches are reaching their limits.  

“Historically, the semiconductor industry has focused on reducing the size of transistors to increase integration density. But we are reaching a quantum mechanical limit and the cost is skyrocketing,” said KAUST Associate Professor Xiaohang Li, who led the study and runs the KAUST Advanced Semiconductor Laboratory. “To continue advancing, we must look beyond planar scaling; stacking transistors vertically is a promising solution.” 

Microchip fabrication often requires temperatures of several hundred degrees Celsius, which can damage the bottom layers of the chip as new ones are added. In the KAUST process, no fabrication step exceeded 150oC, and most steps were completed at nearly room temperature.  

The surface of the layers must also be as smooth as possible. Modifications in the new design kept the surfaces smoother than previous fabrication processes. For vertical stacking, the layers must be aligned properly for optimal connection. Here, too, the scientists improved the fabrication. 

“In microchip design, it is all about packing more power in less space. By refining multiple steps in the fabrication, we provide a blueprint for scaling vertically and increasing functional density far beyond today's limits,” said postdoctoral researcher Saravanan Yuvaraja, first author of the paper. KAUST Professor Martin Heeney and Adjunct Professor Thomas Anthopoulos also contributed to the study. 

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[Press-News.org] Scientists smash record in stacking semiconductor transistors for large-area electronics
The six stacks of semiconductors for hybrid complementary metal-oxide semiconductor (CMOS) microchips advances miniaturization and topples the previous record of two stack