(Press-News.org) Three innovative design techniques substantially enhance wireless transmitter performance and can boost power efficiency and elevate data rates concurrently, as reported by the researchers from Science Tokyo, Japan. This effectively aligns with the growing demand for speed and efficiency, accelerating the widespread deployment of wireless devices. This enables synergistic operation of wireless electronic devices and better quality of modern life.
Background:
Integrating artificial intelligence (AI) into everyday life requires the interconnectedness of all electronic devices via a technology called the Internet of Things (IoT). The rapid expansion of the IoT market has generated tremendous demand for wireless communications. In this context, transmitters—which send information via radio waves to other devices and users—play a pivotal role. Transmitters must be highly power-efficient as most IoT devices are battery-operated. For AI to process greater amounts of data, transmitters should support elevated data rates, enabling a smarter society.
A widely adopted transmitter type, digital polar transmitters, represent input data in polar coordinates—amplitude and phase—which is then transmitted by precise adjustment of the output radio wave’s polar coordinates. However, determining these polar coordinates relies on the COordinate Rotation DIgital Computer (CORDIC), a power-hungry circuit block. CORDIC generates multi-bit amplitude and phase signals that require corresponding modulators. Due to manufacturing defects, these suffer from linearity issues, limiting data rates, making it challenging to balance efficiency and data rate. Enhancing one often compromises the other; for example, while digital pre-distortion (DPD)—a popular linearity calibration technique—can resolve linearity problems for higher data rate, it consumes additional power.
Overview of Research Achievements:
In a recent study, a research team from the Institute of Science Tokyo (Science Tokyo), led by Professor Kenichi Okada, sought to address these problems by developing a CORDIC-less polar transmitter architecture using three innovative design techniques, leading to simultaneous enhancement of power efficiency and data rates. They published this work in the Proceedings of the 2025 IEEE International Solid-State Circuits Conference (ISSCC).
According to Okada, “The first proposed technique employs Delta-Sigma Modulators (DSMs) to re-encode the input data. Instead of directly calculating the polar coordinates of the input x and y signals, two DSMs convert them into 3-level signals. Because these 3-level outputs yield only nine distinct amplitude-phase combinations, a simple nine-state look-up table (LUT) can effectively determine the amplitude and phase.” By avoiding the power-hungry CORDIC and reducing the bit count for amplitude and phase (2-bit amplitude and 3-bit phase), this approach facilitates the use of linear amplitude and phase modulation techniques.
The second and third proposed techniques enable linear amplitude and phase modulation. In conventional multi-bit amplitude and phase modulation schemes, device matching plays a major role in accurately generating intermediate values between zero and the peak relies. However, mismatches arising during this production disrupt the modulation linearity.
In the second proposed technique, the 2-bit amplitude signal is further quantized to 1-bit, preventing increased in-band noise. The 1-bit amplitude controls the transmitter output to toggle between zero and peak amplitudes without any intermediate states, facilitating complete linearity in the transmitter’s amplitude.
In the third proposed technique, since the phase control code has only 3-bits, eight phases separated by 45° each are required. Rather than interpolating phases from 0° to 360°, by leveraging the rising and falling edges of a square wave running at four times the carrier frequency, the eight phases were generated. Multiplexing the different edges of the square wave forms the output phase. These proposed techniques ensure the linearity of both amplitude and phase modulation, eliminating power-intensive calibration procedures. The team tested their ideas by implementing the proposed digital transmitter using a 65nm CMOS process and compared its performance with other state-of-the-art designs.
“By applying these techniques, we achieved top-tier power efficiency and data rates among conventional transmitters, without compromising one for the other, thanks to our CORDIC-less polar transmitter architecture,” concludes Okada.
This innovative architecture can thus spur technological advancements across numerous applications that require transmitters.
This work is partially supported by National Institute of Information and Communications Technology (NICT) in Japan (JPJ012368C00801).
Conference Name: 2025 IEEE International Solid-State Circuits Conference (ISSCC)
Date and Venue: February 16-20, 2025, San Francisco, CA
Presentation Session: Session 5: Front-End Circuits for High-Performance Transceivers
Presentation Time: February 17, 3:35 PM (local time, PST)
Presentation Title: A Power-Efficient CORDIC-less Digital Polar Transmitter Using 1b DSM-Based PA Supporting 256-QAM
Okada Laboratory
https://www.ssc.pe.titech.ac.jp/en/
About Institute of Science Tokyo (Science Tokyo)
Institute of Science Tokyo (Science Tokyo) was established on October 1, 2024, following the merger between Tokyo Medical and Dental University (TMDU) and Tokyo Institute of Technology (Tokyo Tech), with the mission of “Advancing science and human wellbeing to create value for and with society.”
https://www.isct.ac.jp/en
END
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